1. Technical Field
The present invention relates to an information processing device, an arithmetic processing method, an electronic apparatus, and the like.
2. Related Art
In recent years, a processor (in a broad sense, an information processing device) is incorporated in every apparatus in daily use. The processor is required to be small in size, low in cost, low in power consumption, high in function, and high in performance. Various techniques for realizing increases in function and performance of the processor have been examined. As one of the techniques, there is a method of reducing an instruction set of the processor.
The method of reducing the instruction set is equivalent to a technical idea of RISC (Reduced Instruction Set Computer) architecture with respect to a processor having CISC (Complex Instruction Set Computer) architecture. In other words, instructions to be decoded are limited to simple ones and simplified by reducing the instruction set to realize an increase in speed.
When the instruction set is reduced, the number of bits of an operation code representing an instruction can be reduced. Then, there are advantages that the number of bits for designating a register called, for example, operand can be increased to increase the number of registers and arithmetic processing and branching processing can be increased in speed because a maximum value that can be embedded in an instruction as an immediate value is increased.
On the other hand, there are various sizes in numerical values treated by the processor. In an example of the popular C language, data of sizes such as 8 bits (e.g., Char type), 16 bits (e.g., Short type), 32 bits (e.g., int type and long type), and 64 bits (e.g., long type) are treated. When the number of bits increases, a representable data range increases and overflow of an operation result less easily occurs. On the other hand, a capacity of a memory that stores data increases and an increase in circuit size of an arithmetic unit and an increase in power consumption are caused. Therefore, it is desirable that the processor is capable of applying arithmetic processing to data of various sizes and performs processing in data size of the number of bits optimum for the arithmetic processing.
In general, the bit width of an arithmetic unit is fixed in a processor. However, various inventions for efficiently performing arithmetic processing for data having plural bit widths have been proposed. For example, JP-A-8-292876 discloses a technique for dividing an arithmetic logical arithmetic circuit into two to make it possible to simultaneously execute two kinds of arithmetic processing having half-word length. For example, JP-A-10-91439 discloses a processor in which a register having predetermined bit length is divided into two to be capable of operating in parallel.
However, in the technique disclosed in JP-A-8-292876, a computer program or the like needs to explicitly designate “one word” processing or “half ward” processing to instruct execution of only one of these kinds of processing. Similarly, in the technique disclosed in JP-A-10-91439, it is necessary to cause the processor to exclusively operate to process data having predetermined bit length as “one word” or two “half words”. Therefore, with the techniques disclosed in JP-A-8-292876 and JP-A-10-91439, code efficiency of a computer program regarded as effective for a reduction in power consumption and a reduction in cost of an apparatus mounted with the processor cannot be improved.